1. Field of Use
This invention relates to diagnostic apparatus and more particularly to apparatus for testing and verifying the operation of apparatus associated with the semiconductor memory modules of a memory system.
It has become well known to construct memory systems comprising a plurality of memory modules from arrays of metal oxide semiconductor (MOS) chips. Such chips require periodic refreshing of the charges stored therein to prevent the loss of information. Similarly, read or write operations involve alterations of the stored changes representative of information. In order to increase the reliability of such memory systems, it is well known to include in such systems error detection and correction apparatus for detecting and correcting errors within such semiconductor modules.
Recently, manufacturers of such MOS dynamic random access memory chips have noted that high density memory chips lack immunity to soft errors resulting from ionizing alpha particles. To overcome this problem, some manufacturers have improved the structures of the chips so as to provide a high degree of immunity to soft errors. While this approach reduces the likeliness of such soft errors, such errors still can occur which can give rise to uncorrectable error conditions.
This type of problem has been overcome by including soft error rewrite hardware apparatus in a MOS dynamic memory system which in conjunction with the refresh utilization circuits and error detection and correction (EDAC) circuits of the dynamic memory system writes corrected versions of the information read out from each location at a predetermined rate. The additional apparatus includes counter control circuits which are synchronized from the same timing source which synchronizes the refresh and initialize address counter circuits. The counter control circuits count with a modulus one less than a maximum count for generating a sequence of counts at which enable the selection of row and column addresses for rewriting all of the locations with error free information during a corresponding number of cycles of operation at the predetermined rate. The predetermined rate is selected to be much slower than the refresh rate so as to minimize interference with normal memory operations.
This additional apparatus is the subject of the copending patent application of Robert B. Johnson and Chester M. Nibby, Jr. tilted "Soft Error Rewrite Control System" referenced as a related application herein. For further information regarding this apparatus, reference may be made to this application.
2. Prior Art
In such systems, it becomes essential to ensure through the use of checking and diagnostic procedures that each portion of the memory system is operating properly. A very important aspect of such procedures involves the checking and verification of such error detection and correction apparatus in addition to any other apparatus included within the memory system for increased reliability.
Because of the increase in the complexity of the memory system that it has become desirable to include circuits within the system which facilitate the verification of the proper operation of the different portions of the memory system under the control of a data processing unit. One such arrangement, invented by Chester M. Nibby, Jr. et al, is described in U.S. Pat. No. 3,814,922 which is assigned to the same assignee as named herein.
The arrangement of U.S. Pat. No. 3,814,922 includes a maintenance status register and associated apparatus for manipulation and storing of information involving errors detected in the memory module associated with a data processing unit. Errors detected in the memory module are entered in prescribed positions of the maintenance status register. The presence and nature of a detected error is signalled to the data processing unit, which responds in a manner appropriate to the nature of the error. The data processing unit has access to the contents of the maintenance status register in order to localize the malfunction and determine the availability of the memory module.
Another mode of operation is provided for checking the logic circuits associated with the apparatus for refreshing the volatile data contained in the memory elements. The operation of the logic circuit is verified under control of the data processing unit.
It is seen that the above arrangement enables verification of logic circuits which control the operations of a memory module during different modes of operation. However, there is no provision for directly verifying apparatus which is used for enhancing the reliability of memory module operations.
Accordingly, it is a primary object of the present invention to provide apparatus for verifying the operation of soft error hardware apparatus associated with the memory modules of a memory system.
It is a more specific object of the present invention to provide apparatus for verifying the operation of soft error control apparatus within a minimum of time and with the introduction of a minimum of additional apparatus.